1. Field of the Invention
This invention relates to a semiconductor memory device capable of storing a plurality of data items in a single memory cell.
2. Description of the Related Art
A NAND flash memory has been developed as a nonvolatile semiconductor memory device. In a NAND flash memory, all of or half of the cells arranged in the row direction are connected to bit lines in a one-to-one correspondence. Each bit line is connected to a latch circuit which stores write data and read data. All of or half of the cells (e.g., 2 to 4 KB of cells) arranged in the row direction are written to or read from simultaneously. In an erase operation, the threshold voltage of a memory cell is made negative and electrons are injected into the memory cell by a write operation, thereby making the threshold voltage positive. The erase operation is carried out in blocks, each block (e.g., 1 MB of cells) including a plurality of NAND strings (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
If a memory cell has been erased deeply in an erase operation and the threshold voltage of the memory cell is made negative strongly, great stress is placed on the cell, which causes the cell to deteriorate further. This causes a problem: the data retention characteristic gets worse. Therefore, the cell has to be erased as shallowly as possible. However, if the erase voltage is made lower, the following problem arises: when a NAND flash memory is written to and erased repeatedly, it is erased less easily. To avoid this problem, there is a method of, when erasing the NAND flash memory shallowly, making the erase voltage lower and stepping up the erase voltage gradually, thereby erasing the memory gradually. In this case, however, the following problems arise: the erase time increases and stress is placed on the cells because erase pulses are applied to the cells many times.
To overcome this problem, the following technique has been developed: the number of erased cells in a cell erase verify operation is checked and, if the number of erased cells is smaller than a predetermined number, the erase pulse width or erase voltage is increased and erasing is done, and if the number of erased cells is larger than the predetermined number, the erase pulse width or erase voltage is decreased and erasing is done, thereby keeping constant the erase speed varying according to the process or operating environment to prevent excessive erasure (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-25283).
Furthermore, since an erase verify operation is carried out on a NAND string basis, its verify accuracy is lower than when reading is done on a one-word line basis. To overcome this problem, a nonvolatile semiconductor memory device capable of shortening erase time and assuring high reliability has been developed (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-157890).
However, those are not sufficient and a still shorter erase time and a still higher erase verify accuracy have been desired.